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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16507-1E
32-bit Proprietary Microcontroller
CMOS
FR60Lite MB91260B Series
MB91263B/MB91F264B
s DESCRIPTION
The MB91260B series is a 32-bit RISC microcontroller designed by Fujitsu for embedded control applications which require high-speed processing. The CPU is used the FR family and the compatibility of FR60Lite.
s FEATURES
* FR60Lite CPU * 32-bit RISC, load/store architecture with a five-stage pipeline * Maximum operating frequency : 33 MHz (oscillation frequency 4.192 MHz, oscillation frequency 8-multiplier (PLL clock multiplication method) * 16-bit fixed length instructions (basic instructions) * Execution speed of instructions : 1 instruction per cycle * Memory-to-memory transfer, bit handling, barrel shift instructions, etc : Instructions suitable for embedded applications * Function entry/exit instructions, multiple-register load/store instructions : Instructions adapted for C-language (Continued)
s PACKAGES
100-pin plastic QFP 100-pin plastic LQFP
(FTP-100P-M06)
(FTP-100P-M05)
MB91260B Series
(Continued) * Register interlock function : Facilitates coding in assembler. * Built-in multiplier with instruction-level support * 32 bit multiplication with sign : 5 cycles * 16 bit multiplication with sign : 3 cycles * Interrupt (PC, PS save) : 6 cycles, 16 priority levels * Harvard architecture allowing program access and data access to be executed simultaneously * FR family instruction compatible * Internal peripheral functions * Capacity of internal ROM and ROM type MASK ROM : 128 KB (MB91263B) FLASH ROM : 256 KB (MB91F264B) * Capacity of internal RAM : 8 KB * A/D converter (sequential comparison type) * Resolution : 10 bits : 2 ch x 2 units, 8 ch x 1 unit * Conversion time : 1.2 s (Minimum conversion time system clock at 33 MHz) 1.35 s (Minimum conversion time system clock at 20 MHz) * External interrupt input : 10 ch * Bit search module (for REALOS) Function for searching the MSB in each word for the first 1-to-0 inverted bit position * UART (Full-duplex double buffer) : 3 ch Selectable parity On/Off Asynchronous (start-stop synchronized) or clock-synchronous communications selectable Internal timer for dedicated baud rate (U-Timer) on each channel External clock can be used as transfer clock Error detection function for parity, frame and overrun errors * 8/16-bit PPG timer : 16 ch (at 8-bit) / 8 ch (at 16-bit) * Reload timer : 3 ch (with cascade mode, without output of reload timer 0) * Free-run timer : 1 ch * PWC timer : 2 ch * Input capture : 4 ch (interface with free-run timer) * Output compare : 6 ch (interface with free-run timer) * Waveform generator Various waveforms which are generated by using output compare, 16-bit PPG timer 0 and 16-bit dead timer * SUM of products macro (simple DSP) RAM : instruction RAM 256 x 16-bit XRAM 64 x 16-bit YRAM 64 x 16-bit Execution of 1 cycle product addition (16-bit x 16-bit + 40 bits) Operation results are extracted rounded from 40 to 16 bits * DMAC (DMA Controller) : 5 ch Operation of transfer and activation by internal peripheral interrupts and software * Watchdog timer * Low Power Consumption Mode Sleep/stop function * Package : QFP-100, LQFP-100 * Technology : CMOS 0.35 m * Power supply : 1-power supply [Vcc = 4.0 V to 5.5 V]
2
MB91260B Series
s PIN ASSIGNMENT
(TOP VIEW)
P22/SCK0 P21/SOT0 P20/SIN0 P17 P16/PPG15 X0 X1 VSS VCC P15/PPG14 P14/PPG13 P13/PPG12 P12/PPG11 P11/PPG10 P10/PPG9 P07/PPG8 P06/PPG7 P05/PPG6 P04/PPG5 P03/PPG4 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
P23/SIN1 P24/SOT1 P25/SCK1 P26/INT6 P27/INT7 P50 P51/TIN0 P52/TIN1 P53/TIN2 P54/INT0 P55/INT1 P56/INT2 P57/INT3 PG0/CKI/INT4 PG1/PPG0/INT5 PG2 VCC VSS C PG3/SIN2 PG4/SOT2 PG5/SCK2 P40 P41 P42 P43 P44 P45 P46 P47
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P02/PPG3 P01/PPG2 P00/PPG1 INIT MD0 MD1 MD2 NMI P77/ADTG2 P76/ADTG1 P75/ADTG0 P74/PWI1 VSS VCC P73/PWI0 P72/DTTI P71/TOT2 P70/TOT1 P63/INT9 P62/INT8 P61/IC3 P60/IC2 P37/IC1 P36/IC0 P35/RTO5 P34/RTO4 P33/RTO3 P32/RTO2 P31/RTO1 P30/RTO0
PE1/AN11 PE0/AN10 AVRH2 ACC AVCC AVRH1 AVSS PD1/AN9 PD0/AN8 AVRH0 PC7/AN7 PC6/AN6 PC5/AN5 PC4/AN4 PC3/AN3 PC2/AN2 PC1/AN1 PC0/AN0 VCC VSS
(FPT-100-M06)
(Continued)
3
MB91260B Series
(Continued)
(TOP VIEW)
P25/SCK1 P26/INT6 P27/INT7 P50 P51/TIN0 P52/TIN1 P53/TIN2 P54/INT0 P55/INT1 P56/INT2 P57/INT3 PG0/CKI/INT4 PG1/PPG0/INT5 PG2 VCC VSS C PG3/SIN2 PG4/SOT2 PG5/SCK2 P40 P41 P42 P43 P44
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P24/SOT1 P23/SIN1 P22/SCK0 P21/SOT0 P20/SIN0 P17 P16/PPG15 X0 X1 VSS VCC P15/PPG14 P14/PPG13 P13/PPG12 P12/PPG11 P11/PPG10 P10/PPG9 P07/PPG8 P06/PPG7 P05/PPG6 P04/PPG5 P03/PPG4 P02/PPG3 P01/PPG2 P00/PPG1
INIT MD0 MD1 MD2 NMI P77/ADTG2 P76/ADTG1 P75/ADTG0 P74/PWI1 VSS VCC P73/PWI0 P72/DTTI P71/TOT2 P70/TOT1 P63/INT9 P62/INT8 P61/IC3 P60/IC2 P37/IC1 P36/IC0 P35/RTO5 P34/RTO4 P33/RTO3 P32/RTO2
4
P45 P46 P47 PE1/AN11 PE0/AN10 AVRH2 ACC AVCC AVRH1 AVSS PD1/AN9 PD0/AN8 AVRH0 PC7/AN7 PC6/AN6 PC5/AN5 PC4/AN4 PC3/AN3 PC2/AN2 PC1/AN1 PC0/AN0 VCC VSS P30/RTO0 P31/RTO1
(FPT-100-M05)
MB91260B Series
s PIN DESCRIPTION
Pin Circuit QFP LQFP name type SIN1 1 99 P23 SOT1 2 100 P24 SCK1 3 1 P25 D D D Pin no. Description UART1 data input terminal. When use the terminal as data input of UART1, set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function is always valid. UART1 data output terminal. This function becomes valid when data output of UART1 is set to enabled. General purpose input/output port. This function becomes valid when data output of UART1 is set to disabled. UART1 clock input/output terminal. This function becomes valid when clock input/output is set to enabled. General purpose input/output port. This function becomes valid when clock input/output is set to disabled. External interrupt input terminal. When use the terminal as external interrupt input, set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function is always valid. External interrupt input terminal. When use the terminal as external interrupt input, set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function is always valid. C General purpose input/output port. External trigger input terminal of reload timer 0. When use the terminal as trigger input, set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function is always valid. External trigger input terminal of reload timer 1. When use the terminal as external trigger input, set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function is always valid.
INT6 4 2 P26 E
INT7 5 3 P27 6 4 P50 TIN0 7 5 P51 C E
TIN1 8 6 P52 C
(Continued)
5
MB91260B Series
Pin Circuit type QFP LQFP name TIN2 9 7 P53 C
Pin no.
Description External trigger input terminal of reload timer 2. When use the terminal as external trigger input, set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function is always valid. External interrupt input terminal. When use the terminal as external interrupt input, set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function is always valid. External interrupt input terminal. When use the terminal as external interrupt input, set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function is always valid. External interrupt input terminal. When use the terminal as external interrupt input, set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function is always valid. External interrupt input terminal. When use the terminal as external interrupt input, set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function is always valid. External clock input terminal for free-run timer. When use the terminal as external clock input of free-run timer, set the corresponding data direction resister (DDR) to input.
INT0 10 8 P54 E
INT1 11 9 P55 E
INT2 12 10 P56 E
INT3 13 11 P57 E
CKI
14
12
INT4
E
External interrupt input terminal. When use the terminal as external interrupt input, set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function is always valid.
PG0
(Continued)
6
MB91260B Series
Pin Circuit QFP LQFP name type PPG0
Pin no.
Description Output terminal of PPG timer 0. This function becomes valid when output of PPG timer 0 is set to enabled.
15
13
INT5
E
External interrupt input terminal. When use the terminal as external input, output of PPG timer 0 is set to disabled, and set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function becomes valid when output of PPG temer 0 is set to disabled.
PG1 16 14 PG2 SIN2 20 18 PG3 SOT2 21 19 PG4 SCK2 22 20 PG5 23 24 25 26 27 28 29 30 21 22 23 24 25 26 27 28 P40 P41 P42 P43 P44 P45 P46 P47 AN11 31 29 PE1 G C C C C C C C C D D D C
General purpose input/output port. UART2 data input terminal. When use the terminal as data input of UART2, set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function is always valid. UART2 data output terminal. This function becomes valid when data output of UART2 is set to enabled. General purpose input/output port. This function becomes valid when data output of UART2 is set to disabled. UART2 clock input/output terminal. This function becomes valid when clock input/output of UART2 is set to enabled. General purpose input/output port. This function becomes valid when clock input/output of UART2 is set to disabled. General purpose input/output port. General purpose input/output port. General purpose input/output port. General purpose input/output port. General purpose input/output port. General purpose input/output port. General purpose input/output port. General purpose input/output port. Analog input terminal of A/D converter. This function becomes valid when set the corresponding AICR2 resister to analog input. General purpose input/output port. This function becomes valid when set the corresponding AICR2 resister to port.
(Continued)
7
MB91260B Series
Pin Circuit QFP LQFP name type AN10 32 30 PE0 G
Pin no.
Description Analog input terminal of A/D converter. This function becomes valid when set the corresponding AICR2 resister to analog input. General purpose input/output port. This function becomes valid when set the corresponding AICR2 resister to port. Analog input terminal of A/D converter. This function becomes valid when set the corresponding AICR1 resister to analog input. General purpose input/output port. This function becomes valid when set the corresponding AICR1 resister to port. Analog input terminal of A/D converter. This function becomes valid when set the corresponding AICR1 resister to analog input. General purpose input/output port. This function becomes valid when set the corresponding AICR1 resister to port. Analog input terminal of A/D converter. This function becomes valid when set the corresponding AICR0 resister to analog input. General purpose input/output port. This function becomes valid when set the corresponding AICR0 resister to port. Analog input terminal of A/D converter. This function becomes valid when set the corresponding AICR0 resister to analog input. General purpose input/output port. This function becomes valid when set the corresponding AICR0 resister to port. Analog input terminal of A/D converter. This function becomes valid when set the corresponding AICR0 resister to analog input. General purpose input/output port. This function becomes valid when set the corresponding AICR0 resister to port. Analog input terminal of A/D converter. This function becomes valid when set the corresponding AICR0 resister to analog input. General purpose input/output port. This function becomes valid when set the corresponding AICR0 resister to port. Analog input terminal of A/D converter. This function becomes valid when set the corresponding AICR0 resister to analog input. General purpose input/output port. This function becomes valid when set the corresponding AICR0 resister to port.
AN9 38 36 PD1 G
AN8 39 37 PD0 G
AN7 41 39 PC7 G
AN6 42 40 PC6 G
AN5 43 41 PC5 G
AN4 44 42 PC4 G
AN3 45 43 PC3 G
(Continued)
8
MB91260B Series
Pin Circuit type QFP LQFP name AN2 46 44 PC2 G
Pin no.
Description Analog input terminal of A/D converter. This function becomes valid when set the corresponding AICR0 resister to analog input. General purpose input/output port. This function becomes valid when set the corresponding AICR0 resister to port. Analog input terminal of A/D converter. This function becomes valid when set the corresponding AICR0 resister to analog input. General purpose input/output port. This function becomes valid when set the corresponding AICR0 resister to port. Analog input terminal of A/D converter. This function becomes valid when set the corresponding AICR0 resister to analog input. General purpose input/output port. This function becomes valid when set the corresponding AICR0 resister to port. Waveform generator output terminal of multi-function timer. This terminal outputs waveform set at the waveform generator. This function becomes valid when waveform generator output of multi-function timer is set to enabled. General purpose input/output port. This function becomes valid when output of waveform generator is set to disabled. Waveform generator output terminal of multi-function timer. This terminal outputs waveform set at the waveform generator. This function becomes valid when waveform generator output of multi-function timer is set to enabled. General purpose input/output port. This function becomes valid when output of waveform generator is set to disabled. Waveform generator output terminal of multi-function timer. This terminal outputs waveform set at the waveform generator. This function becomes valid when waveform generator output of multi-function timer is set to enabled. General purpose input/output port. This function becomes valid when output of waveform generator is set to disabled. Waveform generator output terminal of multi-function timer. This terminal outputs waveform set at the waveform generator. This function becomes valid when waveform generator output of multi-function timer is set to enabled. General purpose input/output port. This function becomes valid when output of waveform generator is set to disabled.
AN1 47 45 PC1 G
AN0 48 46 PC0 G
RTO0 51 49 P30 J
RTO1 52 50 P31 J
RTO2 53 51 P32 J
RTO3 54 52 P33 J
(Continued)
9
MB91260B Series
Pin Circuit QFP LQFP name type RTO4 55 53 P34 J
Pin no.
Description Waveform generator output terminal of multi-function timer. This terminal outputs waveform set at the waveform generator. This function becomes valid when waveform generator output of multi-function timer is set to enabled. General purpose input/output port. This function becomes valid when output of waveform generator is set to disabled. Waveform generator output terminal of multi-function timer. This terminal outputs waveform set at the waveform generator. This function becomes valid when waveform generator output of multi-function timer is set to enabled. General purpose input/output port. This function becomes valid when output of waveform generator is set to disabled. Trigger input terminal of input capture 0. When use the terminal as trigger input of input capture, set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function is always valid. Trigger input terminal of input capture 1. When use the terminal as trigger input of input capture, set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function is always valid. Trigger input terminal of input capture 2. When use the terminal as trigger input of input capture, set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function is always valid. Trigger input terminal of input capture 3. When use the terminal as trigger input of input capture, set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function is always valid. External interrupt input terminal. When use the terminal as external input, set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function is always valid. External interrupt input terminal. When use the terminal as external input, set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function is always valid.
RTO5 56 54 P35 J
IC0 57 55 P36 D
IC1 58 56 P37 D
IC2 59 57 P60 D
IC3 60 58 P61 D
INT8 61 59 P62 E
INT9 62 60 P63 E
(Continued)
10
MB91260B Series
Pin no. QFP LQFP
Pin name TOT1
Circuit type
Description Output terminal of reload timer 1. This function becomes valid when reload timer output is set to enabled. General purpose input/output port. This function becomes valid when reload timer output is set to disabled. Output terminal of reload timer 2. This function becomes valid when reload timer output is set to enabled. General purpose input/output port. This function becomes valid when reload timer output is set to disabled. Outputcontrol input terminal of waveform generator output terminal RTO0 to RTO5 of multi-function timer. This function becomes valid when DTTI input is set to enabled by waveform generator of multi-function timer. General purpose input/output port. This function is always valid. Pulse width counter input terminal of PWC timer 0. This function becomes valid when pulse width counter input of PWC timer 0 is set to enabled. General purpose input/output port. This function is always valid. Pulse width counter input terminal of PWC timer 1. This function becomes valid when pulse width counter input of PWC timer 1 is set to enabled. General purpose input/output port. This function is always valid. External trigger input terminal of A/D converter 0. When use the external trigger as activation factor of A/D convertor, set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function is always valid. External trigger input terminal of A/D converter 1. When use the external trigger as activation factor of A/D convertor, set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function is always valid. External trigger input terminal of A/D converter 2. When use the external trigger as activation factor of A/D convertor, set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function is always valid.
63
61 P70 TOT2
C
64
62 P71
C
DTTI 65 63 P72 D
PWI0 66 64 P73 D
PWI1 69 67 P74 D
ADTG0 70 68 P75 C
ADTG1 71 69 P76 C
ADTG2 72 70 P77 73 71 NMI H C
NMI (Non Maskable Interrupt) input terminal.
(Continued)
11
MB91260B Series
Pin no. QFP 74 75 76 77
Pin Circuit LQFP name type 72 73 74 75 MD2 MD1 MD0 INIT PPG1 K K K I
Description Mode terminal 2. Set operating mode. Connect to VCC or VSS. Mode terminal 1. Set operating mode. Connect to VCC or VSS. Mode terminal 0. Set operating mode. Connect to VCC or VSS. External reset input terminal. Output terminal of PPG timer 1. This function becomes valid when output of PPG timer 1 is set to enabled. General purpose input/output port. This function becomes valid when output of PPG timer 1 is set to disabled. Output terminal of PPG timer 2. This function becomes valid when output of PPG timer 2 is set to enabled. General purpose input/output port. This function becomes valid when output of PPG timer 2 is set to disabled. Output terminal of PPG timer 3. This function becomes valid when output of PPG timer 3 is set to enabled. General purpose input/output port. This function becomes valid when output of PPG timer 3 is set to disabled. Output terminal of PPG timer 4. This function becomes valid when output of PPG timer 4 is set to enabled. General purpose input/output port. This function becomes valid when output of PPG timer 4 is set to disabled. Output terminal of PPG timer 5. This function becomes valid when output of PPG timer 5 is set to enabled. General purpose input/output port. This function becomes valid when output of PPG timer 5 is set to disabled. Output terminal of PPG timer 6. This function becomes valid when output of PPG timer 6 is set to enabled. General purpose input/output port. This function becomes valid when output of PPG timer 6 is set to disabled. Output terminal of PPG timer 7. This function becomes valid when output of PPG timer 7 is set to enabled. General purpose input/output port. This function becomes valid when output of PPG timer 7 is set to disabled.
78
76 P00 PPG2
C
79
77 P01 PPG3
C
80
78 P02 PPG4
C
81
79 P03 PPG5
C
82
80 P04 PPG6
C
83
81 P05 PPG7
C
84
82 P06
C
(Continued)
12
MB91260B Series
Pin no. QFP LQFP
Pin name PPG8
Circuit type
Description Output terminal of PPG timer 8. This function becomes valid when output of PPG timer 8 is set to enabled. General purpose input/output port. This function becomes valid when output of PPG timer 8 is set to disabled. Output terminal of PPG timer 9. This function becomes valid when output of PPG timer 9 is set to enabled. General purpose input/output port. This function becomes valid when output of PPG timer 9 is set to disabled. Output terminal of PPG timer 10. This function becomes valid when output of PPG timer 10 is set to enabled. General purpose input/output port. This function becomes valid when output of PPG timer 10 is set to disabled. Output terminal of PPG timer 11. This function becomes valid when output of PPG timer 11 is set to enabled. General purpose input/output port. This function becomes valid when output of PPG timer 11 is set to disabled. Output terminal of PPG timer 12. This function becomes valid when output of PPG timer 12 is set to enabled. General purpose input/output port. This function becomes valid when output of PPG timer 12 is set to disabled. Output terminal of PPG timer 13. This function becomes valid when output of PPG timer 13 is set to enabled. General purpose input/output port. This function becomes valid when output of PPG timer 13 is set to disabled. Output terminal of PPG timer 14. This function becomes valid when output of PPG timer 14 is set to enabled. General purpose input/output port. This function becomes valid when output of PPG timer 14 is set to disabled. Main clock oscillation output terminal. Main clock oscillation input terminal. Output terminal of PPG timer 15. This function becomes valid when output of PPG timer 15 is set to enabled. General purpose input/output port. This function becomes valid when output of PPG timer 15 is set to disabled. General purpose input/output port. UART0 data input terminal. When use the terminal as data input of UART0, set the corresponding data direction resister (DDR) to input. General purpose input/output port. This function is always valid.
85
83 P07 PPG9
C
86
84 P10 PPG10
C
87
85 P11 PPG11
C
88
86 P12 PPG12
C
89
87 P13 PPG13
C
90
88 P14 PPG14
C
91
89 P15
C
94 95
92 93
X1 X0 PPG15
A A
96
94 P16
C
97
95
P17 SIN0
C
98
96 P20
D
(Continued)
13
MB91260B Series
(Continued) Pin no.
QFP
Pin Circuit LQFP name type SOT0
Description UART0 data output terminal. This function becomes valid when data output of UART0 is set to enabled. General purpose input/output port. This function becomes valid when data output of UART0 is set to disabled. UART0 clock input/output terminal. This function becomes valid when clock input/output of UART0 is set to enabled. General purpose input/output port. This function becomes valid when clock input/output of UART0 is set to disabled.
99
97 P21 SCK0
D
100
98 P22
D
* Power supply and GND pins Pin no. QFP 18, 50, 68, 93 17, 49, 67, 92 35 33 36 40 37 19 34 LQFP 16, 48, 66, 91 15, 47, 65, 90 33 31 34 38 35 17 32
Pin name Vss Vcc AVcc AVRH2 AVRH1 AVRH0 AVss C ACC
Description GND pins. Apply equal potential to all of the pins. Power supply pin. Apply equal potential to all of the pins. Analog power supply pin for A/D converter. Analog reference power supply pin for A/D converter 2. Analog reference power supply pin for A/D converter 1. Analog reference power supply pin for A/D converter 0. Analog GND pin for A/D converter. Condencer connection pin for internal regulator. Condencer connection pin for analog.
14
MB91260B Series
s I/O CIRCUIT TYPE
Type
X1
Circuit type
Remarks * Oscillation circuit * Oscillation feedback resistance : approx. 1 M
Clock input
A
X0
Standby control Pull-up control * CMOS level output * CMOS level input. * With standby control * With Pull-up control * Pull-up resistance value = approx. 50 k (Typ) * IOL = 4 mA Digital input Standby control Pull-up control * CMOS level output * CMOS level hysteresis input. * With standby control * With Pull-up control * Pull-up resistance value = approx. 50 k (Typ) * IOL = 4 mA Digital input Standby control
P-ch
Digital output
P-ch
C
R N-ch
Digital output
P-ch
Digital output
P-ch
D
R N-ch
Digital output
(Continued)
15
MB91260B Series
Type
Circuit type Pull-up control
Remarks * CMOS level output * CMOS level hysteresis input. * Without standby control * With Pull-up control * Pull-up resistance value = approx. 50 k (Typ) * IOL = 4 mA Digital input * Analog/CMOS level input/output pin * CMOS level output * CMOS level input. (attached with standby control) * Analog input (Analog input is enabled when AICR's corresponding bit is set to "1".) * IOL = 4 mA
Digital output
P-ch P-ch
E Digital output
R N-ch
Digital output
P-ch
Digital output G
R N-ch
Digital input Standby control Analog input
* CMOS level hysteresis input. * Without standby control
P-ch
H
R N-ch
Digital input
(Continued)
16
MB91260B Series
(Continued) Type
Circuit type
Remarks * CMOS level hysteresis input.
P-ch
P-ch
* With pull-up resistor * Pull-up resistance value = approx. 50 k (Typ) * Without standby control
I
R N-ch
Digital input * CMOS level output * CMOS level hysteresis input. Digital output
P-ch
* With standby control Digital output * IOL = 12 mA
J
R
N-ch
Digital input Standby control * CMOS level input. * Without standby control
P-ch
K
R N-ch
Digital input
17
MB91260B Series
s HANDLING DEVICES
* Preventing Latchup Latch-up may occur in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output pin or if an above-rating voltage is applied between VCC and VSS. A latchup, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, be very careful not to exceed the maximum rating. * Treatment of Unused Input Pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pullup or pull-down resistor. * About power supply pins In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However you must connect the pins to external a same potential power supply and a ground line to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. The power pins should be connected to VCC and VSS of this device at the lowest possible impedance from the current supply source. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 F between VCC and VSS near this device. * About Crystal oscillator circuit Noise near the X0 and X1 pin may cause the device to malfunction. Design the circuit board so that X0 and X1, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended to design the PC board artwork with the X0 and XI pins surrounded by ground plane because stable operation can be expected with such a layout. * Mode pins (MD0 to MD2) These pins should be connected directly to VCC or VSS. To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that the distance between the mode pins and VCC or VSS is as short as possible and the connection impedance is low. * Operation at start-up Be sure to execute setting initialized reset (INIT) with INIT pin immediately after start-up. Also, in order to provide a delay while the oscillator circuit stabilize immediately after start-up, maintain the "L" level input to the INIT pin for the required stabilization wait time. (For INIT via the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value.) * About oscillation input at power on When turning the power on, maintain clock input until the device is released from the oscillation stabilization wait state.
18
MB91260B Series
* Caution operation during PLL clock mode Even if the oscillator comes off or the clock input stops with the PLL clock selected for this device, the device may continue to operate at the free-run frequency of the PLL's internal self-oscillating oscillator circuit. Performance of this operation, however, cannot be guaranteed. * External clock When external clock is selected, the opposite phase clock to X0 pin must be supplied to X1 pin simultaneously. If the STOP mode (oscillation stop mode) is used simultaneously, the X1 pin is stopped with the "H" output. So, when STOP mode is specified, approximately 1 k of resistance should be added externally to avoid the conclift of output. The following figure shows using an external clock.
X0
X1
MB91260B series
Using an external clock
* C pin A bypass capacitor of approximately 0.1 F should be connected the C pin for built-in regulator.
C
MB91260B series
VSS
0.1 F
GND
* ACC pin A capacitor of approximately 0.1 F should be inserted between the ACC pin and the AVcc pin as this product has built-in A/D convertor.
ACC
MB91260B series
AVSS
0.1 F
19
MB91260B Series
* Clock control block Take the oscillation stabilization wait time during Low level input to the INIT pin. * Switch shared port function To switch between the use as a port and the use as a dedicated pin, use the port function register (PFR). * Low Power Consumption Mode (1) To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the TBCR: or time-base counter control register) and be sure to use the following seaquence (LDI #value_of_standby, R0) : Value_of standby is write data to STCR. (LDI STB LDUB LDUB NOP NOP NOP NOP NOP In addition, please set I flag, ILM, and ICR to diverge to the interruption handler that is the return factor after the standby returns. (2) Please do not do the following when the monitor debugger is used. * Break point setting for above instruction lines * Step execution for above instruction lines * Notes on the PS register As the PS register is processed by some instructions in advance, exception handling below may cause the interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register to be updated. As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs operations before and after the EIT as specified in either case. 1. The following operations are performed when the instruction followed by a DIV0U/DIV0S instruction results in : (a) acceptance of a user interrupt or NMI, (b) step execution, or (c) a break at a data event or emulator menu. (1) The D0 and D1 flags are updated in advance. (2) An EIT handling routine (user interrupt, NMI, or emulator) is executed. (3) Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are updated to the same values as in (1). 2. The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed to enable interruptions when a user interrupt or NMI trigger even has occurred. (1) The PS register is updated in advance. (2) An EIT handling routine (user interrupt, NMI) is executed. (3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as in (1). #_STCR, R12) R0, @R12 @R12, R0 @R12, R0 : _STCR is address (481H) of STCR. : Writing to standby control register (STCR) : STCR read for synchronous standby : Dummy re-read of STCR : NOP x 5 for arrangement of timing
20
MB91260B Series
* Watch dog timer The watchdog timer built in this model monitors a program that it defers a reset within a certain period of time. The watchdog timer resets the CPU if the program runs out of controls, preventing the reset defer function from being executed. Once the function of the watchdog timer is enabled, therefore, the watchdog timer keeps on operating programs until it resets the CPU. As an exception, the watchdog timer defers a reset timing automatically under the condition in which the CPU stops program execution.
21
MB91260B Series
s NOTE ON DEBUGGER
* Step execution of RETI command If an interrupt occurs frequently during step execution, the corresponding interrupt handling routine is executed repeatedly after step execution. This will prevent the main routine and low-interrupt-level programs from being executed. Do not execute step of RETI instruction for escape. Disable the corresponding interrupt and execute debugger when the corresponding interrupt handling routine no longer needs debugging. * Operand break Do not apply a data event break to access to the area containing the address of a system stack pointer. * Execution in an unused area of FLASH memory Accidentally executing an instruction in an unused area of FLASH memory (with data placed at 0XFFFF) prevents breaks from being accepted. To prevent this, the code event address mask function of the debugger should be used to cause a break when accessing an instruction in an unused area. * Power-on debugging All of the following three conditions must be satisfied when the power supply is turned off by power-on debugging. (1) The time for the user power to fall from 0.9 VCC to 0.5 VCC is 25 s or longer. Note : In a dual-power system, VCC indicates the external I/O power supply voltage. (2) CPU operating frequency must be higher than 1 MHz. (3) During execution of user program * Interrupt handler for NMI request (tool) Add the following program to the interrupt handler to prevent the device from malfunctioning in case the factor flag to be set only in response to a break request from the ICE is set, for example, by an adverse effect of noise to the DSU pin while the ICE is not connected. Enable to use the ICE while adding this program. Additional location Next interrupt handler Interrupt source : NMI request (tool) Interrupt number Offset Address TBR is default Additional program STM (R0, R1) LDI LDI STB LDM RETI 22 #B00H, R0; #0, R1 R1, @R0 (R0, R1) : Clear the break factor register. : B00H is the address of DSU break factor register. : #13 (decimal) , 0DH (hexa decimal) : 3C8H : 000FFFC8H
MB91260B Series
s BLOCK DIAGRAM
FR60 Lite CPU core
32
32 DMAC 5 ch
Bit search
SUM of products macro
ROM 128 KB/ FLASH 256 KB
Bus converter
RAM 8 KB
32
X0, X1 MD0 ~ MD2 INIT
32 16 Adapter Clock control
16
Port I/F
PORT
Interrupt controller 10 ch External interrupt
3 ch reload timer
TIN0 ~ TIN2 TOT1, TOT2
INT0 ~ INT9 NMI
SIN0 ~ SIN2 SOT0 ~ SOT2 SCK0 ~ SCK2 3 ch UART
2 ch PWC timer
PWI0, PWI1
8 ch 8/16 PPG timer 3 ch U timer
PPG0 ~ PPG15
AVCC ADTG0 AN0 ~ AN7 AVRH0 ADTG1 AVRH1 AN8, AN9 ADTG2 AVRH2 AN10, AN11
Multi-function timer 8 ch input 8/10 bit A/D-0 2 ch input 8/10 bit A/D-1 2 ch input 8/10 bit A/D-2 Free-run timer 1 ch Input capture 4 ch Output compare 6 ch
RTO0 ~ RTO5 CKI IC0 ~ IC3
Waveform generator
DTTI
23
MB91260B Series
s MEMORY SPACE
1. Memory space
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access. * Direct Addressing Areas The following address space areas are used as I/O areas. These areas are called direct addressing areas, in which the address of an operand can be specified directly during an instruction. The size of directly addressable areas depends on the data size to be being accessed as follows. byte data access half word data access word data access : 000-0FFH : 000-1FFH : 000-3FFH
2. Memory Map
MB91F264B Single chip mode
0000 0000H I/O 0000 0400H I/O 0001 0000H 0003 E000H 0000 0000H
MB91263B Single chip mode Direct addressing area Refer to I/O Map Direct addressing area Refer to I/O Map
I/O 0000 0400H I/O 0001 0000H 0003 E000H
Access disallowed Internal RAM 8 KB
Access disallowed Internal RAM 8 KB Access disallowed
0004 0000H
0004 0000H
Access disallowed
000C 0000H
000E 0000H
0010 0000H
Internal RAM 256 KB Access disallowed
0010 0000H
Internal RAM 128 KB Access disallowed
FFFF FFFFH
FFFF FFFFH
Each mode is set depending on the mode vector fetched after the INIT signal is nagated. (Refer to MODE SETTINGS for mode setting.)
24
MB91260B Series
s MODE SETTINGS
The FR family uses mode pins (MD2 to MD0) and a mode data to set the operation mode.
1. Mode Pins
The MD2, MD1, and MD0 pins specify how the mode vector fetch and reset vector fetch is performed. Setting is prohibited other than that shown in the following table. Mode Pins MD2 0 1 MD1 0 0 MD0 0 0 Reset vector access area Internal
Mode name Internal ROM mode vector Flash serial write mode
Remarks
2. Mode data
Data written to the internal mode register (MODR) by a mode vector fetch is called mode data. After an operation mode has been set in the mode register, the device operates in the operation mode. The mode data is set by all reset source. User programs cannot set data to the mode register.

31 0 30 0 29 0 28 0 27 0 26 1 25 1 24 1
Operation mode setting bits [bit31-24] Reserved bit Be sure to set this bit to "00000111". Operation is not guaranteed when any value other than "00000111" is set.
3. Note
Mode data set in the mode vector must be placed as byte data at 0X000FFFF8. Use the highest byte from bit 31 to bit 24 for placement as the FR family uses the big endian method for byte endian. 31 Incorrect 0x000FFFF8 Correct 0x000FFFF8 0x000FFFFC 24 23 XXXXXXXX Mode Data 16 15 XXXXXXXX XXXXXXXX 87 Mode Data XXXXXXXX 0
XXXXXXXX XXXXXXXX
Reset Vector
25
MB91260B Series
s I/O MAP
This shows the location of the various peripheral resource registers in the memory space. Register +0 PDR0 [R/W]B XXXXXXXX +1 PDR1 [R/W]B XXXXXXXX +2 PDR2 [R/W]B XXXXXXXX +3 PDR3 [R/W]B XXXXXXXX
Address 000000H
Block Port data register
Read/write attribute, Access unit (B : byte, H : half word, W : word) Initial value after a reset Register name (First-column register at address 4n; second-column register at address 4n + 2) Location of left-most register (When using word access, the register in column 1 is in the MSB side of the data.) Note : Initial values of register bits are represented as follows : "1" : Initial Value : " 1 " "0" : Initial Value : " 0 " "X" : Initial Value : " undefined " "-" : No physical register at this location
26
MB91260B Series
Address 000000H 000004H 000008H 00000CH 000010H 000014H to 00003CH 000040H 000044H 000048H 00004CH 000050H 000054H 000058H 00005CH 000060H 000064H 000068H 00006CH 000070H 000074H
Register +0
PDR0 [R/W] B XXXXXXXX PDR4 [R/W] B XXXXXXXX
+1
PDR1 [R/W] B XXXXXXXX PDR5 [R/W] B XXXXXXXX
+2
PDR2 [R/W] B XXXXXXXX PDR6 [R/W] B ----XXXX
+3
PDR3 [R/W] B XXXXXXXX PDR7 [R/W] B XXXXXXXX
Block
PDRC [R/W] B XXXXXXXX PDRG [R/W] B --XXXXXX PDRD [R/W] B ------XX PDRE [R/W] B ------XX
Port data register Reserved
ELVR0 [R/W] B, H, W 00000000 00000000

EIRR0 [R/W] B, H, W 00000000 DICR [R/W] B, H, W -------0
ENIR0 [R/W] B, H, W 00000000 HRCL [R/W, R] B, H, W 0--11111
External interrupt (INT0 to INT7) Delay interrupt/ Hold request Reload timer 0
TMRLR0 [W] H, W XXXXXXXX XXXXXXXX
TMR0 [R] H, W XXXXXXXX XXXXXXXX TMCSR0 [R/W, R] B, H, W ---00000 00000000 TMR1 [R] H, W XXXXXXXX XXXXXXXX TMCSR1 [R/W, R] B, H, W ---00000 00000000 TMR2 [R] H, W XXXXXXXX XXXXXXXX TMCSR2 [R/W, R] B, H, W ---00000 00000000
TMRLR1 [W] H, W XXXXXXXX XXXXXXXX
TMRLR2 [W] H, W XXXXXXXX XXXXXXXX
Reload timer 1
SSR0 [R/W, R] B, H, W 00001000
Reload timer 2
SIDR0 [R]/SODR0[W] SCR0 [R/W] B, H, W SMR0 [R/W, W] B, H, W B, H, W 00000100 00--0-0XXXXXXXX DRCL0 [W] B -------UTIMC0 [R/W] B 0--00001 SMR1 [R/W] B, H, W 00--0-0UTIMC1 [R/W] B 0--00001 SMR2 [R/W] B, H, W 00--0-0UTIMC2 [R/W] B 0--00001
UART0 U-timer 0 UART1 U-timer 1 UART2 U-timer 2
UTIM0 [R] H / UTIMR0 [W] H 00000000 00000000 SSR1 [R/W, R] B, H, W 00001000
SIDR1 [R]/SODR1[W] SCR1 [R/W] B, H, W B, H, W 00000100 XXXXXXXX DRCL1 [W] B --------
UTIM1 [R] H / UTIMR1 [W] H 00000000 00000000 SSR2 [R/W, R] B, H, W 00001000
SIDR2 [R]/SODR2[W] SCR2 [R/W] B, H, W B, H, W 00000100 XXXXXXXX DRCL2 [W] B --------
UTIM2 [R] H / UTIMR2 [W] H 00000000 00000000
(Continued)
27
MB91260B Series
Address 000078H 00007CH 000080H 000084H 000088H 00008CH 000090H
Register +0
ADCH0 [R/W] B, H, W XX000000 ADCS0 [R/W, W] B, H, W 00000X00 ADCH1 [R/W] B, H, W XXXX0XX0 ADCS1 [R/W, W] B, H, W 00000X00 ADCH2 [R/W] B, H, W XXXX0XX0 ADCS2 [R/W, W] B, H, W 00000X00
+1
ADMD0 [R/W] B, H, W 00001111
+2
+3
Block
A/D converter 0/ AICR0
ADCD01 [R] B, H, W ADCD00 [R] B, H, W XXXXXXXX XXXXXXXX AICR0 [R/W] B, H, W 00000000
ADMD1 [R/W] B, H, W 00001111
ADCD11 [R] B, H, W ADCD10 [R] B, H, W XXXXXXXX XXXXXXXX AICR1 [R/W] B, H, W ------00
ADMD2 [R/W] B, H, W 00001111
A/D converter 1/ AICR1
ADCD21 [R] B, H, W ADCD20 [R] B, H, W XXXXXXXX XXXXXXXX AICR2 [R/W] B, H, W ------00
A/D converter 2/ AICR2
OCCPBH0, OCCPBL0[W]/ OCCPH0, OCCPL0[R] H, W 00000000 00000000 OCCPBH2, OCCPBL2[W]/ OCCPH2, OCCPL2 [R] H, W 00000000 00000000 OCCPBH4, OCCPBL4[W]/ OCCPH4, OCCPL4 [R] H, W 00000000 00000000 OCSH1 [R/W] B, H, W X1100000 OCSH5 [R/W] B, H, W X1100000 OCSL0 [R/W] B, H, W 00001100 OCSL4 [R/W] B, H, W 00001100
OCCPBH1, OCCPBL1[W]/ OCCPH1, OCCPL1 [R] H, W 00000000 00000000 OCCPBH3, OCCPBL3[W]/ OCCPH3, OCCPL3 [R] H, W 00000000 00000000 OCCPBH5, OCCPBL5[W]/ OCCPH5, OCCPL5 [R] H, W 00000000 00000000 OCSH3 [R/W] B, H, W X1100000 OCMOD [R/W] B, H, W XX000000 OCSL2 [R/W] B, H, W 00001100
000094H
000098H
OCU
00009CH
0000A0H
0000A4H
CPCLRBH, CPCLRBL[W]/ CPCLRH, CPCLRL[R] H, W 11111111 11111111 TCCSH [R/W] B, H, W 00000000 TCCSL [R/W] B, H, W 01000000
TCDTH, TCDTL [R/W] H, W 00000000 00000000
0000A8H 0000ACH 0000B0H 0000B4H 0000B8H
ADTRGC [R/W] B, H, W XXXX0000
free-run timer
IPCPH0, IPCPL0 [R] H, W XXXXXXXX XXXXXXXX IPCPH2, IPCPL2 [R] H, W XXXXXXXX XXXXXXXX PICSH01 [W] B, H, W 000000-EIRR1 [R/W] B, H, W ------00 PICSL01 [R/W] B, H, W 00000000 ENIR1 [R/W] B, H, W ------00
IPCPH1, IPCPL1 [R] H, W XXXXXXXX XXXXXXXX IPCPH3, IPCPL3 [R] H, W XXXXXXXX XXXXXXXX ICSH23 [R] B, H, W XXXXXX00 ICSL23 [R/W] B, H, W 00000000
ICU
ELVR1 [R/W] B, H, W -------- ----0000
External interrupt (INT8, INT9)
(Continued)
28
MB91260B Series
Address 0000BCH 0000C0H 0000C4H 0000C8H 0000CCH 0000D0H 0000D4H to 0000DCH 0000E0H 0000E4H 0000E8H 0000ECH to 000FCH 000100H 000104H 000108H 00010CH 000110H 000114H 000118H 00011CH 000120H
Register +0 +1 +2 +3
TMRRH0, TMRRL0 [R/W] H, W XXXXXXXX XXXXXXXX TMRRH2, TMRRL2 [R/W] H, W XXXXXXXX XXXXXXXX DTCR0 [R/W] B, H, W 00000000 DTCR1 [R/W] B, H, W 00000000 SIGCR1 [R/W] B, H, W 10000000 TMRRH1, TMRRL1 [R/W] H, W XXXXXXXX XXXXXXXX
Block
DTCR2 [R/W] B, H, W 00000000

SIGCR2 [R/W] B, H, W XXXXXXX1 ADCOMP1 [R/W] H, W 00000000 00000000
Waveform generator
ADCOMP0 [R/W] H, W 00000000 00000000 ADCOMP2 [R/W] H, W 00000000 00000000 PWCSR0 [R/W, R] B, H, W 00000000 00000000 PWCSR1 [R/W, R] B, H, W 00000000 00000000 PDIVR0 [R/W] B, H, W XXXXX000 PRLH0 [R/W] B, H, W XXXXXXXX PRLH2 [R/W] B, H, W XXXXXXXX PPGC0 [R/W] B, H, W 0000000X PRLH4 [R/W] B, H, W XXXXXXXX PRLH6 [R/W] B, H, W XXXXXXXX PPGC4 [R/W] B, H, W 0000000X PRLH8 [R/W] B, H, W XXXXXXXX PRLL0 [R/W] B, H, W XXXXXXXX PRLL2 [R/W] B, H, W XXXXXXXX PPGC1 [R/W] B, H, W 0000000X PRLL4 [R/W] B, H, W XXXXXXXX PRLL6 [R/W] B, H, W XXXXXXXX PPGC5 [R/W] B, H, W 0000000X PRLL8 [R/W] B, H, W XXXXXXXX
ADCOMPC [R/W] B, H, W XXXXX000
A/D COMP
Reserved
PWCR0 [R] H, W 00000000 00000000 PWCR1 [R] H, W 00000000 00000000 PDIVR1 [R/W] B, H, W XXXXX000
PWC
Reserved
PRLL1 [R/W] B, H, W XXXXXXXX PRLL3 [R/W] B, H, W XXXXXXXX PPGC3 [R/W] B, H, W 0000000X PRLL5 [R/W] B, H, W XXXXXXXX PRLL7 [R/W] B, H, W XXXXXXXX PPGC7 [R/W] B, H, W 0000000X PRLL9 [R/W] B, H, W XXXXXXXX PRLL11 [R/W] B, H, W XXXXXXXX PPGC11 [R/W] B, H, W 0000000X
PRLH1 [R/W] B, H, W XXXXXXXX PRLH3 [R/W] B, H, W XXXXXXXX PPGC2 [R/W] B, H, W 0000000X PRLH5 [R/W] B, H, W XXXXXXXX PRLH7 [R/W] B, H, W XXXXXXXX PPGC6 [R/W] B, H, W0000000X PRLH9 [R/W] B, H, W XXXXXXXX PRLH11 [R/W] B, H, W XXXXXXXX PPGC10 [R/W] B, H, W 0000000X
PPG
PRLH10 [R/W] B, H, W PRLL10 [R/W] B, H, W XXXXXXXX XXXXXXXX PPGC8 [R/W] B, H, W 0000000X PPGC9 [R/W] B, H, W 0000000X
(Continued)
29
MB91260B Series
Address 000124H 000128H 00012CH 000130H 000134H 000138H to 0001FCH 000200H 000204H 000208H 00020CH 000210H 000214H 000218H 00021CH 000220H 000224H 000228H to 00023CH 000240H 000244H to 000398H
Register +0 +1 +2 +3
PRLL13 [R/W] B, H, W XXXXXXXX PRLL15 [R/W] B, H, W XXXXXXXX
Block
PRLH12 [R/W] B, H, W PRLL12 [R/W] B, H, W PRLH13 [R/W] B, H, W XXXXXXXX XXXXXXXX XXXXXXXX PRLH14 [R/W] B, H, W PRLL14 [R/W] B, H, W PRLH15 [R/W] B, H, W XXXXXXXX XXXXXXXX XXXXXXXX
PPGC12 [R/W] B, H, W PPGC13 [R/W] B, H, W PPGC14 [R/W] B, H, W PPGC15 [R/W] B, H, W 0000000X 0000000X 0000000X 0000000X TRG [R/W] B, H, W 00000000 00000000 REVC [R/W] B, H, W 00000000 00000000
PPG

GATEC [R/W] B, H, W XXXXXX00
Reserved
DMACA0 [R/W] B, H, W *1 00000000 00000000 00000000 00000000 DMACB0 [R/W] B, H, W 00000000 00000000 00000000 00000000 DMACA1 [R/W] B, H, W*1 00000000 00000000 00000000 00000000 DMACB1 [R/W] B, H, W 00000000 00000000 00000000 00000000 DMACA2 [R/W] B, H, W *1 00000000 00000000 00000000 00000000 DMACB2 [R/W] B, H, W 00000000 00000000 00000000 00000000 DMACA3 [R/W] B, H, W *1 00000000 00000000 00000000 00000000 DMACB3 [R/W] B, H, W 00000000 00000000 00000000 00000000 DMACA4 [R/W] B, H, W *1 00000000 00000000 00000000 00000000 DMACB4 [R/W] B, H, W 00000000 00000000 00000000 00000000 DMACR [R/W] B 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX Reserved
DMAC
DMAC
Reserved
(Continued)
30
MB91260B Series
Address 00039CH 0003A0H 0003A4H 0003A8H 0003ACH 0003B0H 0003B4H 0003B8H to 0003ECH 0003F0H 0003F4H 0003F8H 0003FCH 000400H 000404H 000408H 00040CH 000410H 000414H to 00041CH 000420H 000424H 000428H 00042CH 000430H
Register +0 DSP-PC [R/W] XXXXXXXX +1 DSP-CSR [R/W, R, W] 00000000 +2 +3
Block
DSP-LY [R/W] XXXXXXXX XXXXXXXX DSP-OT1 [R] XXXXXXXX XXXXXXXX DSP-OT3 [R] XXXXXXXX XXXXXXXX DSP-OT5 [R] XXXXXXXX XXXXXXXX DSP-OT7 [R] XXXXXXXX XXXXXXXX Sum of products
DSP-OT0 [R] XXXXXXXX XXXXXXXX DSP-OT2 [R] XXXXXXXX XXXXXXXX DSP-OT4 [R] XXXXXXXX XXXXXXXX DSP-OT6 [R] XXXXXXXX XXXXXXXX
Reserved
BSD0 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDR0 [R/W] B 00000000 DDR4 [R/W] B 00000000 DDRC [R/W] B 00000000 DDRG [R/W] B --000000 DDR1 [R/W] B 00000000 DDR5 [R/W] B 00000000 DDRD [R/W] B ------00 PFR0 [R/W] B 00000000 PFRG [R/W] B --00--0PFR1 [R/W] B -0000000 PFR2 [R/W] B --00-00 PFR7 [R/W] B ------00 Port function register DDR2 [R/W] B 00000000 DDR6 [R/W] B ----0000 DDRE [R/W] B ------00 DDR3 [R/W] B 00000000 DDR7 [R/W] B 00000000 Reserved Data direction register
Bit search
(Continued)
31
MB91260B Series
Address 000434H to 00043CH 000440H 000444H 000448H 00044CH 000450H 000454H
Register +0 +1
ICR00 [R/W, R] B, H, W ICR01 [R/W, R] B, H, W ICR02 [R/W, R] B, H, W ICR03 [R/W, R] B, H, W ----1111 ----1111 ----1111 ----1111 ICR04 [R/W, R] B, H, W ICR05 [R/W, R] B, H, W ICR06 [R/W, R] B, H, W ICR07 [R/W, R] B, H, W ----1111 ----1111 ----1111 ----1111 ICR08 [R/W, R] B, H, W ICR09 [R/W, R] B, H, W ICR10 [R/W, R] B, H, W ICR11 [R/W, R] B, H, W ----1111 ----1111 ----1111 ----1111 ICR12 [R/W, R] B, H, W ICR13 [R/W, R] B, H, W ICR14 [R/W, R] B, H, W ICR15 [R/W, R] B, H, W ----1111 ----1111 ----1111 ----1111 ICR16 [R/W, R] B, H, W ICR17 [R/W, R] B, H, W ICR18 [R/W, R] B, H, W ICR19 [R/W, R] B, H, W ----1111 ----1111 ----1111 ----1111 ICR20 [R/W, R] B, H, W ICR21 [R/W, R] B, H, W ICR22 [R/W, R] B, H, W ICR23 [R/W, R] B, H, W ----1111 ----1111 ----1111 ----1111
+2
+3
Block
Reserved
Interrupt
ICR24 [R/W, R] B, H, W ICR25 [R/W, R] B, H, W ICR26 [R/W, R] B, H, W ICR27 [R/W, R] B, H, W controller 000458H ----1111 ----1111 ----1111 ----1111
00045CH 000460H 000464H 000468H 00046CH 000470H to 00047CH 000480H 000484H 000488H to 0005FCH 000600H 000604H 000608H 00060CH
ICR28 [R/W, R] B, H, W ICR29 [R/W, R] B, H, W ICR30 [R/W, R] B, H, W ICR31 [R/W, R] B, H, W ----1111 ----1111 ----1111 ----1111 ICR32 [R/W, R] B, H, W ICR33 [R/W, R] B, H, W ICR34 [R/W, R] B, H, W ICR35 [R/W, R] B, H, W ----1111 ----1111 ----1111 ----1111 ICR36 [R/W, R] B, H, W ICR37 [R/W, R] B, H, W ICR38 [R/W, R] B, H, W ICR39 [R/W, R] B, H, W ----1111 ----1111 ----1111 ----1111 ICR40 [R/W, R] B, H, W ICR41 [R/W, R] B, H, W ICR42 [R/W, R] B, H, W ICR43 [R/W, R] B, H, W ----1111 ----1111 ----1111 ----1111 ICR44 [R/W, R] B, H, W ICR45 [R/W, R] B, H, W ICR46 [R/W, R] B, H, W ICR47 [R/W, R] B, H, W ----1111 ----1111 ----1111 ----1111
RSRR [R/W] B, H, W 10000000 CLKR [R/W] B, H, W 00000000 STCR [R/W] B, H, W 00110011 WPR [W] B, H, W XXXXXXXX TBCR [R/W] B, H, W 00XXXX00 DIVR0 [R/W] B, H, W 00000011 CTBR [W] B, H, W XXXXXXXX DIVR1 [R/W] B, H, W 00000000
Reserved
Clock control unit
PCR0 [R/W] B 00000000 PCR4 [R/W] B 00000000 PCR1 [R/W] B 00000000 PCR5 [R/W] B 00000000 PCR2 [R/W] B 00000000 PCR6 [R/W] B ----0000 PCR3 [R/W] B 00-----PCR7 [R/W] B 00000000
Reserved
Pull-up Control

(Continued)
32
MB91260B Series
Address 000610H 000614H to 000FFCH 001000H 001004H 001008H 00100CH 001010H 001014H 001018H 00101CH 001020H 001024H 001028H to 006FFCH 007000H 007004H 007008H 00700CH 007010H 007014H to 00BFFCH
Register +0 PCRG [R/W] B --000000 +1 DMASA0 [R/W] W 00000000 00000000 00000000 00000000 DMADA0 [R/W] W 00000000 00000000 00000000 00000000 DMASA1 [R/W] W 00000000 00000000 00000000 00000000 DMADA1 [R/W] W 00000000 00000000 00000000 00000000 DMASA2 [R/W] W 00000000 00000000 00000000 00000000 DMADA2 [R/W] W 00000000 00000000 00000000 00000000 DMASA3 [R/W] W 00000000 00000000 00000000 00000000 DMADA3 [R/W] W 00000000 00000000 00000000 00000000 DMASA4 [R/W] W 00000000 00000000 00000000 00000000 DMADA4 [R/W] W 00000000 00000000 00000000 00000000 FLCR [R/W] 0110X000 FLWC [R/W] 00000011*2 +2 +3
Block Pull-up Control Reserved
DMAC
Reserved
FLASH
Reserved
(Continued)
33
MB91260B Series
(Continued)
Address 00C000H to 00C07CH 00C080H to 00C0FCH 00C100H to 00C2FCH 00C300H to 00FFFCH Register +0 +1 +2 +3 Block
X-RAM (coefficient RAM) [R/W] 64 x 16 bit Y-RAM (variable RAM) [R/W] 64 x 16 bit I-RAM (instruction RAM) [R/W] 256 x 16 bit Reserved Sum of products
*1 : The lower 16 bits (DTC[15: 0]) of DMACA0 to DMACA4 cannot be accessed in bytes. *2 : The initial value of 1FLWC (7004H) is "00010011B" on EVA tool. Writing "00000011B" on the evaluation model has no effect on its operation. Notes : * Do not excute Read Modify Write instructions on registers having a write-only bit. * Data is undefined in reseved or (-) area.
34
MB91260B Series
s INTERRUPT VECTOR
Interrupt source Reset Mode vector System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction Instruction break exception Operand break trap Step trace trap NMI request (tool) Undefined instruction exception NMI request External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 Reload timer 0 Reload timer 1 Reload timer 2 UART0(Reception completed) UART0 (RX completed) DTTI DMAC0 (end, error) DMAC1 (end, error) DMAC2/3/4 (end, error) Interrupt number 10 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 Interrupt level 15 (FH) fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H 37CH TBR default address 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H 000FFF7CH RN 6 7 8 9 10 0 3
(Continued)
35
MB91260B Series
Interrupt source UART1(Reception completed) UART1 (RX completed) UART2 (Reception completed) UART2 (RX completed) SUM of products macro PPG0 PPG1 PPG2/3 PPG4/5/6/7 PPG8/9/10/11/12/13/14/15 External interrupt 8/9 Waveform0 (under flow) Waveform1 (under flow) Waveform2 (under flow) Timebase timer overflow Free-run timer (Compare clear) Free-run timer (zero detection) A/D0 A/D1 A/D2 PWC0 (measurment completed) PWC1 (measurment completed) PWC0 (overflow) PWC1 (overflow) ICU0 (capture) ICU1 (capture) ICU2/3 (capture) OCU0/1 (match) OCU2/3 (match) OCU4/5 (match) Delay interrupt source bit System reserved (Used by REALOS) System reserved (Used by REALOS)
Interrupt number 10 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 16 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41
Interrupt level ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
Offset 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H
TBR default address 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H
RN 1 4 2 5
(Continued)
36
MB91260B Series
(Continued)
Interrupt source System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Used by INT instruction Interrupt number 10 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 to 255 16 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 to FF Interrupt level Offset 2F4H 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH to 000H TBR default address 000FFEF4H 000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH to 000FFC00H RN
37
MB91260B Series
s PIN STATUS IN EACH CPU STATE
Terms used as the status of pins mean as follows. * Input enabled * Indicates that the input function can be used. * Input 0 fixed * Indicates that the input level has been internally fixed to be 0 to prevent leakage when the input is released. * Output Hi-Z * Means the placing of a pin in a high impedance state by preventing the transistor for driving the pin from driving. * Output is maintained. * Indicates the output in the output state existing immediately before this mode is established. * If the device enters this mode with an internal output peripheral operating or while serving as an output port, the output is performed by the internal peripheral or the port output is maintained, respectively. * State existing immediately before is maintained. * When the device serves for output or input immediately before entering this mode, the device maintains the output or is ready for the input, respectively.
38
MB91260B Series
* List of pin status (single chip mode) Pin no. Pin name Function QFP LQFP 1 2 3 4, 5 99 100 1 2, 3 P23 P24 P25 P26, P27 SIN1 SOT1 SCK1 INT6, INT7
At initializing INIT = L*1 INIT = H*2
At sleep mode
At Stop mode Hi-Z = 0 Hi-Z = 1
Retention Retention of the of the Output Hi-Z/ immediately immediately Input 0 fixed prior state prior state Input enabled Input enabled Input enabled
6 to 9
4 to 7
P50 to P53
Ports
Retention Retention of the of the Output Hi-Z/ immediately immediately Input 0 fixed prior state prior state
10 11 12 13 14 15 16 20 21 22
8 9 10 11 12 13 14 18 19 20
P54 P55 P56 P57 PG0 PG1 PG2 PG3 PG4 PG5
INT0 INT1 INT2 INT3 CKI/INT4 PPG0/INT5 Output Hi-Z/ Output Hi-Z/ Input Input Ports disabled disabled SIN2 SOT2 SCK2 Ports AN11, AN10 AN9, AN8 AN7 to AN0 RTO0 to RTO5 IC0, IC1 IC2, IC3 INT8, INT9 Input enabled Input enabled Input enabled Retention Retention of the of the Output Hi-Z/ immediately immediately Input 0 fixed prior state prior state Input enabled Input enabled Input enabled
23 to 30 21 to 28 P40 to P47 31, 32 38, 39 29, 30 36, 37 PE1, PE0 PD1, PD0 PC7 to PC0
41 to 48 39 to 46
51 to 56 49 to 54 P30 to P35 57, 58 59, 60 61, 62 55, 56 57, 58 59, 60 P36, P37 P60, P61 P62, P63
(Continued)
39
MB91260B Series
(Continued)
P : Selection of general purpose port, F : Selection of specified function At initializing Pin no. At sleep Pin Function mode name QFP LQFP INIT = L*1 INIT = H*2 63, 64 61, 62 P70, P71 65 66 69 70 71 72 73 78 79 80 81 82 83 84 85 86 87 88 89 90 91 96 97 98 99 100 63 64 67 68 69 70 71 76 77 78 79 80 81 82 83 84 85 86 87 88 89 94 95 96 97 98 P72 P73 P74 P75 P76 P77 NMI P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 TOT1, TOT2 DTTI PWI0 PWI1 ADTG0 ADTG1 ADTG2 NMI PPG1 PPG2 PPG3 PPG4 PPG5 PPG6 PPG7 PPG8 PPG9 PPG10 PPG11 PPG12 PPG13 PPG14 PPG15 Ports SIN0 SOT0 SCK0 Retention Retention Output Hi-Z/ output Hi-Z/ of the of the Ouptut Hi-Z/ input disabled input disabled immediately immediately input 0 fixed prior state prior state Input enabled Input enabled Input enabled Input enabled Input enabled Retention Retention Output Hi-Z/ Output Hi-Z/ of the of the Output Hi-Z/ input disabled input disabled immediately immediately Input 0 fixed prior state prior state At Stop mode Hi-Z = 0 Hi-Z = 1
*1 : INIT = L : Indicates the pin status with INIT remaining at the "L" level. *2 : INIT = H : Indicates the pin status existing immediately after INIT transition from "L" to "H" level.
40
MB91260B Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Power supply voltage Analog power supply voltage Analog reference voltage Input voltage Analog pin input voltage Output voltage L level maximum output current L level average output current L level total maximum output current L level total average output current H level maximum output current H level average output current H level total maximum output current H level total average output current Power consumption Symbol VCC AVCC AVRH VI VIA VO IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV Rating Min VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.3 VSS - 0.3 VSS - 0.3 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VCC + 0.3 AVcc + 0.3 VCC + 0.3 10 8 100 50 - 10 -4 - 50 - 20 600 PD 600 360 - 40 Operating temperature Ta - 40 Storage temperature Tstg - 55 + 85 125 C C + 105 C mW Unit V V V V V V mA mA mA mA mA mA mA mA *4 FLASH product MASK product Ta + 85 C MASK product Ta + 105 C *5 MASK product (at single chip operating) FLASH product (at single chip operating) *4 *2 *3 *2 *3 *1 *1 (VSS = AVSS = 0 V) Remarks
*1 : Be careful not to exceed VCC + 0.3 V, for example, when the power is turned on. Be careful not to let AVCC exceed VCC, for example, when the power is turned on. *2 : The maximum output current is the peak value for a single pin. *3 : The average output current is the average current for a single pin over a period of 100 ms. *4 : The total average output current is the average current for all pins over a period of 100 ms. *5 : For use at Ta = +105 C, lower the operating frequency to reduce power consumption. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
41
MB91260B Series
2. Recommended Operating Conditions
Value Min 4.0 VSS + 4.0 AVSS AVSS AVSS - 40 Operating temperature Ta - 40 + 85 C Max 5.5 VSS + 5.5 AVCC AVCC AVCC + 105
(Vss = AVss = 0 V) Unit V V V V V C For A/D converter 0 For A/D converter 1 For A/D converter 2 MASK product (at single chip operation) FLASH product (at single chip operation) Remarks At normal operating
Parameter Power supply voltage Analog power supply voltage Analog reference voltage
Symbol VCC AVCC AVRH0 AVRH1 AVRH2
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
42
MB91260B Series
3. DC Characteristics
Sym bol VIH VIHS VIL VILS VOH
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V) Pin Conditions Value Min 0.8 x Vcc Vcc - 0.4 Vss Vss Vcc - 0.5 Vcc - 0.7 -5 Typ 50 90 60 300 Max Vcc Vcc 0.2 x Vcc Vss + 0.4 0.4 0.6 5 100 80 Unit Remarks V V V V V V V V A k mA mA At SLEEP A pF At STOP
Parameter
"H" level input voltage
Other than hysteresis input pin Hysteresis input pin Other than hysteresis input pin Hysteresis input pin
Input Low Voltage
"H" level output voltage
Other than port 30 VCC = 5.0 V, to 35 IOH = 4.0 mA VCC = 5.0 V, IOH = 8.0 mA
VOH2 Port 30 to 35 VOL
Output Low Voltage
Other than port 30 VCC = 5.0 V, to 35 IOL = 4.0 mA VCC = 5.0 V, IOL = 12 mA VCC = 5.0 V, VSS VI VCC VCC = 5.0 V, 33 MHz VCC = 5.0 V, 33 MHz VCC = 5.0 V, Ta = + 25 C
VOL2 Port 30 to 35 ILI INIT, Pull-up pin VCC
Input leak current
Pullup resistance RPULL ICC Power supply current
ICCS VCC ICCH VCC
Input capacitance
CIN
Other than VCC, VSS, AVCC, AVSS, AVRH0, 1, 2
10
43
MB91260B Series
4. FLASH MEMORY write/erase characteristics
Parameter Sector erase time Chip erase time Byte write time Chip write time Erase/write cycle Conditions Ta = + 25 C, Vcc = 5.0 V Ta = + 25 C, Vcc = 5.0 V Ta = + 25 C, Vcc = 5.0 V Ta = + 25 C, Vcc = 5.0 V Value Min 10,000 Typ 1 10 8 2.1 Max 15 3,600 Unit s s s s Cycle Remarks Not including time for internal writing before deletion. Not including time for internal writing before deletion. Not including system-level overhead time. Not including system-level overhead time.
44
MB91260B Series
5. AC Characteristics
(1) Clock Timing Ratings Sym bol fC Value Min 3.6 83.3 When 4.125 MHz is 2.06* input as the X0 2.06* clock frequency and x8 multiplication is 30.3 set for the PLL of the oscillator circuit. 30.3 278 33 33 485* 485* ns Typ Max 12 (VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V) Pin X0 X1 X0 X1 Conditions Unit MHz Remarks For using the PLL within the self-oscillation enabled range, set the multiplier for the internal clock not to let the operating frequency exceed 33 MHz.
Parameter Clock frequency
Clock cycle time
tC fCP fCPP tCP tCPP
Internal operating clock frequency Internal operating clock cycle time
MHz CPU MHz Peripheral ns ns CPU Peripheral
* : The values assume a gear cycle of 1/16. * Conditions for measuring the clock timing ratings
tC 0.8 VCC 0.2 VCC
Output pin
C = 50 pF
PWH tCF
PWL tCR
45
MB91260B Series
* Operation Assurance Range
VCC (V)
Power supply
5.5
4.0
0 0.25
33
fCP / fCPP (MHz)
Internal clock
* Internal clock setting range
(MHz) 33
CPU (CLKB) :
Internal clock
Peripheral (CLKP) :
16.5
4.125
Oscillation input clock fC = 4.192 MHz (PLL multiplied by 8)
8:8 4:4 1:1
CPU : Divided ratio for peripherals.
Notes : * Oscillation stabilization time of PLL > 600 s * The internal clock gear setting should be within the value shown in clock timing ratings table.
46
MB91260B Series
(2) Reset Input Symbol Conditions
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V) Pin Value Min Oscillation time of oscillator + tC x 10 tC x 10 Max Unit ns ns Remarks
Parameter Init input time (at power-on and STOP mode) Init input time (other than the above)
tINTL
INIT
tINTL
INIT
0.2 VCC
47
MB91260B Series
(3) UART Timing
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V) Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin SCK0 to SCK2 SCK0 to SCK2, SOT0 to SOT2 SCK0 to SCK2, SIN0 to SIN2 SCK0 to SCK2, SIN0 to SIN2 SCK0 to SCK2 SCK0 to SCK2 SCK0 to SCK2, SOT0 to SOT2 SCK0 to SCK2, SIN0 to SIN2 SCK0 to SCK2, SIN0 to SIN2 External shift clock mode Conditions Value Min 8 tCYCP - 80 Internal shift clock mode 100 60 4 tCYCP 4 tCYCP 60 60 Max 80 150 Unit Remarks ns ns ns ns ns ns ns ns ns
Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock H pulse width Serial clock L pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time
Notes : * There are the AC ratings for CLK synchronous mode. * tCYCP indicates the peripheral clock cycle time.
48
MB91260B Series
* Internal shift clock mode
tSCYC
SCK0 to SCK2
VOH VOL VOL
tSLOV
SOT0 to SOT2
VOH VOL
tIVSH VOH VOL
tSHIX VOH VOL
SIN0 to SIN2
* External shift clock mode
tSLSH VOH tSHSL
SCK0 to SCK2
VOL
VOL
VOL
tSLOV
SOT0 to SOT2
VOH VOL
tIVSH VOH VOL
tSHIX VOH VOL
SIN0 to SIN2
49
MB91260B Series
(4) Free-run Timer Clock, PWC Input and Reload Timer Trigger Timing
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V) Max Unit Remarks
Parameter
Symbol tTIWH tTIWL
Pin CKI PWI0, PWI1 TIN0 to TIN2
Conditions
Value Min 4 tCYCP
Input pulse width
ns
Note : tCYCP indicates the peripheral clock cycle time.
tTIWH
tTIWL
50
MB91260B Series
(5) Trigger Input Timing
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V) Symbol tINP tATGX Pin IC0 to IC3 ADTG0 to ADTG2 Conditions Value Min 5 tCYCP 5 tCYCP Max Unit ns ns Remarks
Parameter Input capture trigger input A/D activation trigger input
Note : tCYCP indicates the peripheral clock cycle time.
tATGX, tINP
IC0 to IC3 ADTG0 to ADTG2
51
MB91260B Series
6. Electrical Characteristics for the A/D Converter
Parameter Resolution Total error*1 Linearity error* Differential linearity error*1 Zero transition voltage*1 Full transition voltage*1 Conversion time Analog port Input current Analog input voltage Reference voltage Analog power supply current (analog + digital) reference power supply current (between AVRH and AVSS) Analog input capacitance Inter-channel disparity Symbol VOT VFST IAIN VAIN IA IAH*3 IR AVRHn IRH*3 AN0 to AN11 10 100 4 AVcc Pin AN0 to AN11 AN0 to AN11 AN0 to AN11 AN0 to AN11 AVRHn Value Min -4 - 3.5 -3 Typ Max 10 4 3.5 3
(VCC = AVcc = 5.0 V, VSS = AVSS = 0 V) Unit bit LSB LSB LSB At AVRHn*4 = 5.0 V Remarks
AVss - 3.5 AVss + 0.5 AVss + 4.5 LSB AVRH - 5.5 1.2*2 AVss AVss AVRH - 1.5 2 1 AVRH + 2.5 10 AVRH AVcc 100 LSB S A V V mA Per 1 unit A Per 1 unit
Per 1 unit mA AVRHn*4 = 5.0 V, at AVss = 0 V A pF LSB per 1 unit at STOP
*1 : Measured in the CPU sleep state *2 : Vcc = AVcc = 5.0 V, machine clock at 33 MHz *3 : The current when the CPU is in stop mode and the A/D converter is not operating (at Vcc = AVcc = AVRHn = 5.0 V) *4: AVRHn = AVRH0, AVRH1, AVRH2 Note : The above does not guarantee the inter-unit accuracy. Set the output impedance of the external circuit 2 k.
52
MB91260B Series
Definition of A/D Converter Terms * Resolution : Analog variation that is recognized by an A/D converter. * Linearity error : Zero transition point (00 0000 0000 00 0000 0001) and full-scale transition point. Difference between the line connected (11 1111 1110 11 1111 1111) and actual conversion characteristics. * Differential linearity error : Deviation of input voltage, that is required for changing output code by 1 LSB, from an ideal value. * Total error : This error indicates the difference between actual and ideal values, including the zero transition error/full-scale transition error/linearity error. Total error
3FF 3FE
Actual conversion characteristics
{1 LSB' (N - 1) + 0.5 LSB'}
1.5 LSB'
Digital output
3FD
004 003 002 001 0.5 LSB' AVSS AVRH
(measurement value)
VNT
Actual conversion characteristics Ideal characteristics
Analog input
1LSB' (Ideal value) VOT' (Ideal value) VFST' (Ideal value)
=
AVRH - AVSS 1024
[V] Total error of digital output N
=
VNT - {1 LSB' x (N - 1) + 0.5 LSB'} 1 LSB'
= AVSS + 0.5 LSB' [V]
= AVRH - 1.5 LSB' [V] VNT : A voltage at which digital output transitions from (N + 1) to N.
(Continued)
53
MB91260B Series
(Continued)
Linearity error
3FF 3FE 3FD
Differential linear error
Actual conversion characteristics
{1 LSB (N - 1) + VOT}
N+1
Actual conversion characteristics Ideal characteristics
Digital output
Digital output
(measurement value)
VFST
N
004 003 002 001
(measurement value)
VNT
N-1
VFST
(measurement value) (measurement value)
Actual conversion characteristics Ideal characteristics
N-2
VNT
V0T (measurement Value)
AVSS AVRH AVSS
Actual conversion characteristics
AVRH
Analog input
Analog input VNT - { 1 LSB x (N - 1) + VOT } 1 LSB V (N + 1) T - VNT 1 LSB VFST - VOT 1022
Linearity error in digital output N =
[LSB]
Differential linearity error in digital output = N
-1
[LSB]
1 LSB
=
[V]
VOT : A voltage at which digital output transitions from 000H to 001H. VFST : A voltage at which digital output transitions from 3FEH to 3FFH .
54
MB91260B Series
s EXAMPLE CHARACTERISTICS
"H" Level Output Voltage vs. Power Supply Voltage
6 5 VOL (mV) 4 VOH (V) 3 2 1 0 4.0 4.5 VCC (V) 5.0 5.5 400 350 300 250 200 150 100 50 0 4.0 4.5 VCC (V) 5.0 5.5
"L" Level Output Voltage vs.
Power Supply Voltage
Pull-up Resistor vs. Power Supply Voltage
80 70 60
Power Supply Current vs. Power Supply Voltage
100 90 80 70 ICC (mA) 60 50 40 30 20 10 0 4.0
R (k)
50 40 30 20 10 0 4.0 4.5 VCC (V) 5.0 5.5
4.5 VCC (V)
5.0
5.5
Power Supply Current vs. Internal Operation Frequency (MB91263)
100 90 80 70
ICC (mA)
60 50 40 30 20 10 0 15 20 25 30 35 4.0 V 4.5 V 5.0 V 5.5 V
Internal operation frequency [MHz]
(Continued)
55
MB91260B Series
(Continued)
Power Supply Current (at sleep) vs. Power Supply Voltageage
80 70 60 ICCS (mA) 50 40 30 20 10 0 4.0 4.5 VCC (V) 5.0 5.5 ICCH (A)
Power Supply Current (at stop) vs. Power Supply Voltage
100 90 80 70 60 50 40 30 20 10 0 4.0 4.5 VCC (V) 5.0 5.5
A/D Conversion Block Per 1 Unit (33 MHz) Analog Power Supply Current vs. Power Supply Voltage
2
A/D Conversion Block Per 1 Unit (33 MHz) Reference Voltage Supplying Current vs. Power Supply Voltage
1.0 0.8 IR (mA) 0.6 0.4 0.2
1.5 IA (mA)
1
0.5
0 4.0
4.5 VCC (V)
5.0
5.5
0.0 4.0
4.5 VCC (V)
5.0
5.5
56
MB91260B Series
s ORDERING INFORMATION
Part number MB91F264BPF-G MB91F264BPF-G-E1 MB91F264BPFV-G MB91F264BPFV-G-E1 MB91263BPF-G-xxx-BND MB91263BPF-G-xxx-BNDE1 MB91263BPFV-G-xxx-BND MB91263BPFV-G-xxx-BNDE1 Package 100-pin plastic QFP (FPT-100P-M06) 100-pin plastic LQFP (FPT-100P-M05) 100-pin plastic QFP (FPT-100P-M06) 100-pin plastic LQFP (FPT-100P-M05) Remarks Lead-free Package Lead-free Package Lead-free Package Lead-free Package
57
MB91260B Series
s PACKAGE DIMENSION
100 - pin plastic QFP (FPT-100P-M06)
23.900.40(.941.016)
* 20.000.20(.787.008)
80 51
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
81
50
0.10(.004) 17.900.40 (.705.016)
*14.000.20 (.551.008)
INDEX Details of "A" part
100 31
1
30
0.25(.010) +0.35 3.00 -0.20 +.014 .118 -.008 (Mounting height) 0~8 0.170.06 (.007.002) 0.800.20 (.031.008) 0.880.15 (.035.006) 0.250.20 (.010.008) (Stand off)
0.65(.026)
0.320.05 (.013.002)
0.13(.005)
M
"A"
C
2002 FUJITSU LIMITED F100008S-c-5-5
Dimensions in mm (inches) Note: The values in parentheses are reference values.
(Continued)
58
MB91260B Series
(Continued)
100-pin plastic LQFP (FPT-100P-M05)
16.000.20(.630.008)SQ
* 14.000.10(.551.004)SQ
75 51
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
76
50
0.08(.003) Details of "A" part
INDEX
1.50 -0.10 .059 -.004 (Mounting height)
26
+0.20
+.008
100
0.100.10 (.004.004) (Stand off) 0.25(.010)
0~8 "A" 0.500.20 (.020.008) 0.600.15 (.024.006)
1
25
0.50(.020)
0.200.05 (.008.002)
0.08(.003)
M
0.1450.055 (.0057.0022)
C
2003 FUJITSU LIMITED F100007S-c-4-6
Dimensions in mm (inches) Note: The values in parentheses are reference values.
59
MB91260B Series
FUJITSU LIMITED
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